Integrated circuit (IC) chips are often electrically connected by wires (e.g., gold or aluminum wires) to a leadframe or a substrate in a packaging assembly to provide external signal exchange. Such wires are typically wire bonded to bond pads formed on an IC chip using thermal compression and/or ultrasonic vibration. A wire bonding process exerts thermal and mechanical stresses on a bond pad and on the underlying intermetal dielectric (IMD) layers and structure below the bond pad. The bond pad structure and IMD layers need to be able to sustain these stresses to ensure a good bonding of the wire and to prevent damage to the IC chip.
Prior bond pad structures were fabricated from the bottom to the top layers, which did not allow metal wiring circuitry and semiconductor devices to pass under or be located below the bond pad structure. For a more efficient use of chip area or to reduce the chip size, it is desirable to form semiconductor devices and metal wiring circuitry under the bond pads. This is sometimes referred to as bond over active circuits (BOAC) or circuits under pad (CUP). At the same time, many processes now use low-k and ultra low-k dielectric materials for the IMD layers to reduce RC delay and parasitic capacitances. The general trend in IMD designs is that the dielectric constant (k) tends to decrease from the top downward toward the substrate. However, as the dielectric constant (k) decreases, typically the strength of the dielectric material decreases (as a general rule). Hence, many low-k dielectric materials are highly susceptible to cracking or lack strength needed to withstand some mechanical processes (e.g., wire bonding, CMP). Not only do low-k dielectric materials tend to be relatively weak in compression strength, they also tend to be weak in adhesion strength and shearing strength, which can cause peeling or delamination.
During a typical wire bonding procedure, the bond pad structure must withstand compressive and lateral shear forces during the ball squishing stage of wire bonding. These forces may cause cracking in the relatively weak low-k dielectric layers. The bond pad structure must also withstand pulling and torsional forces while the wire is being pulled from the wire bonding tool relative to the bond pad on the chip. These forces may cause peeling or dislocation of the bond pad structure.
Currently dummy structures are included between and among the active circuit structures to strengthen the layers of the chip. Such dummy structures are typically made from the same materials as the active wiring and bond pad structures and are typically formed simultaneously with the formation of the active wiring and bond pad structures. This has greatly helped in strengthening chips and reduced the likelihood of cracking and peeling.
When the chips are cut from a wafer, the chips again experience large mechanical stresses, such as compressive and shearing stresses. Such stresses can also cause cracking, peeling, delamination, or even relatively large chunks of the chip to be removed. To account for such stresses, street areas reserved for the path of cutting tools are allocated on the wafer between chips. But for maximizing the number of chips per wafer, it is desirable to minimize the width of the streets reserved for cutting area. At the same time, the extensive use of low-k dielectric materials has greatly weakened the IMD layers, which calls for wider streets. To address this issue, seal rings have been implemented. A seal ring is typically a wall like structure formed around the perimeter of the chip. Often the seal ring is made from metal and/or polysilicon while forming other conductive structures in a layer.
There is a need for a bond pad structure that can sustain and better disperse the stresses exerted on it by a wire bonding process and/or a cutting process, for example, that is compatible with the use of low-k dielectric materials for IMD layers, and that will also allow circuitry and devices to be formed under the bond pads.